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Section 3
Board Description
3.1
AT91SAM7S256
Microcontroller
? Incorporates the ARM7TDMI ? ARM ? Thumb ? Processor
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– EmbeddedICE ? In-circuit Emulation, Debug Communication Channel Support
? 256 Kbytes of Internal High-speed Flash, Organized in 1024 Pages of 256 Bytes
– Single Cycle Access at Up to 30 MHz in Worst Case Conditions,
Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed
– Page Programming Time: 4 ms, Including Page Auto-erase, Full Erase Time: 10
ms
– 10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities,
Flash Security Bit
– Fast Flash Programming Interface for High Volume Production
? 64 Kbytes of Internal High-speed SRAM, Single-cycle Access at Maximum Speed
? Memory Controller (MC)
– Embedded Flash Controller, Abort Status and Misalignment Detection
? Reset Controller (RSTC)
– Based on Power-on Reset and Low-power Factory-calibrated Brown-out Detector
– Provides External Reset Signal Shaping and Reset Source Status
? Clock Generator (CKGR)
– Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLL
? Power Management Controller (PMC)
– Software Power Optimization Capabilities, Including Slow Clock Mode (Down to
500 Hz) and Idle Mode
– Three Programmable External Clock Signals
? Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt
Protected
? Debug Unit (DBGU)
– 2-wire UART and Support for Debug Communication Channel interrupt,
Programmable ICE Access Prevention
? Periodic Interval Timer (PIT)
– 20-bit Programmable Counter plus 12-bit Interval Counter
? Windowed Watchdog (WDT)
AT91SAM7S-EK Evaluation Board User Guide
3-1
6112C–ATARM–01-Feb-07
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